Lattice Semiconductor
Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.
- (503) 268-8000
- (503) 268-8169
- 5555 NE Moore Ct,
Hillsboro,, OR 97124
United States
-
product
Build FPGA-based Processor Systems In Minutes
Lattice Propel Design Environment
Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.
-
product
Advanced General Purpose FPGA
CertusPro-NX
*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
-
product
FPGA Design, Meet Easy.
Lattice Diamond Software
Easy Design Exploration – Finding the best solutions often requires evaluating multiple solutions. Lattice Diamond allows for easy design exploration.
-
product
Low Power MIPI Bridging Solution With Integrated Flash
CrossLinkPlus
*Instant-on (< 10 ms) configuration with integrated flash memory*Integrated flash enables flexible reprogramming in the field*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per port*11 programmable, source synchronous I/O pairs for camera and display interfacing*Available in small 3.5 mm x 3.5 mm BGA package with 0.4 mm pitch*Comprehensive library of IP and reference designs, compatible with CrossLink
-
product
Efficiency And Innovation, Squeezed Into One Tiny, Affordable Package
LatticeECP3
*Up to 16 channels at 3.125 Gbps*800 MBps DDR3, 1Gbps LVDS*Up to 586 programmable sysIO buffers with support for PCI Express, Ethernet (GbE, XAUI, & SGMII), HDMI, SMPTE, Serial Rapid I/O, CPRI and JESD204A/B and more*Up to 150 k LUTs and 6.8 Mbits of SRAM*Wide array of packages as small as 10.0 mm x 10.0 mm with power consumption below 0.5 W
-
product
Mature & Discontinued Devices
The product families on this page have been classified as "Mature". In most cases there is a newer technology product family that will better meet the needs of today's system logic designers. Designers working on new designs are strongly encouraged to evaluate the alternative product families listed in the "Use for New Designs" column. Unless a Mature Family has been formally superseded via our Product Change Notification (PCN) procedure Lattice will continue to support existing business for these Mature products. Certain of the products for which the PCN process has been completed have been transferred, as indicated in the table, to Rochester Electronics or Arrow Electronics. Please contact those companies for availability of the products indicated.
-
product
Low Power FPGA Featuring Hardened MIPI D-PHY, LVDS, SLVS, SubLVDS, & Open LDI Bridging
CrossLink
*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY*15 programmable source synchronous I/O pairs for camera and display interfacing*Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch
-
product
PLD For Bridging, Infinitely Reconfigurable I/O Expansion.
MachXO
*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM*SRAM based logic can be reconfigured in milliseconds using JTAG port*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting*Available in TQFP, csBGA, caBGA and ftBGA packages
-
product
Low-Power General Purpose FPGA
Certus-NX
*Up to 39K logic cells, 2.9 Mb embedded memory, 56 18 x 18 multipliers, 192 programmable I/O, one lane of 5 Gbps PCIe, two lanes of 1.25 Gbps SGMII, two ADCs (each 12-bit, 1 MSPS).*Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Instant-on configuration – I/O configures in 3 ms, and full-device as fast as 8 ms.*Available in Commercial, Industrial and Automotive (AEC-Q100 qualified) temperature grades.
-
product
Break The Rules Of Power, Size And Cost In Your Connectivity And Acceleration Applications
ECP5 / ECP5-5G
*Up to 3.2 Gbps SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G*Up to 4 channels per device in dual channel blocks for higher granularity*Enhanced DSP blocks provide 2x resource improvement for symmetrical filters*Single event upset (SEU) mitigation support*Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input/output interfaces
-
product
Manage Power, Thermal & Control Planes In Real Time
Platform Manager 2 & L-ASC10
*Full fault coverage – monitor all rails and temperature nodes*Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders*Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds*Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters*Reliable power & thermal fault detection in hardware, as opposed to software routines
-
product
ML/AI Low Power FPGA
iCE40 UltraPlus
*Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory*Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications*High performance signal processing using DSP blocks with multiply and accumulate functions*Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation*FPGA design tools, demos and reference designs to kick start designs
-
product
Enabling Low Power, High Reliability, And High Performance Design
Lattice Nexus Platform
The Lattice Nexus FPGA platform combines Lattice’s long-standing low power FPGA expertise with leading 28nm FD-SOI semiconductor manufacturing technology. With this platform, Lattice enables the rapid development of multiple device families that deliver low power, high performance, high reliability and small form factor.
-
product
Futureproof Your Control PLD And Bridging Designs
MachXO3
*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
-
product
Integrated Board Power Management Functions For The Forward Thinking Engineer
Power Manager II
*Up to 12 differential voltage sensors with immunity to noise on ground plane*Voltage trimming to within 1%*Ruggedized CPLD with up to 48 macrocells for sequencing and supervisory signal logic*Large operating power supply range (3.3 V + 20% to 3.3 V -15%)*Up to 4 High-Voltage MOSFET Driver Outputs*Voltage Measurement with 10-bit ADC through I2C*Up to 8 On-chip DACs for Margining and Trimming
