Lattice Semiconductor
Lattice Semiconductor (NASDAQ: LSCC) is the low power programmable leader. We solve customer problems across the network, from the Edge to the Cloud, in the growing communications, computing, industrial, automotive and consumer markets. Our technology, long-standing relationships, and commitment to world-class support lets our customers quickly and easily unleash their innovation to create a smart, secure and connected world.
- (503) 268-8000
- (503) 268-8169
- 5555 NE Moore Ct,
Hillsboro,, OR 97124
United States
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Futureproof Your Control PLD And Bridging Designs
MachXO3
*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
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Build FPGA-based Processor Systems In Minutes
Lattice Propel Design Environment
Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.
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Hardware Security For Programmable System Control
Mach-NX
*Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature*Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages*Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC*Configuration of PFR and security functions through Lattice Propel simplifies developer experience*Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies
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ML/AI Low Power FPGA
iCE40 UltraPlus
*Flexible logic architecture with 2800 or 5280 4 input LUTs, customizable I/O, up to 80 kbits of embedded dual port memory and 1 Mbit of embedded single port memory*Ultra-low power advanced process with static current as low as 75 uA and 1-10 mA active current for most applications*High performance signal processing using DSP blocks with multiply and accumulate functions*Soft Neural Network IPs and compiler for flexible Machine Learning/AI implementation*FPGA design tools, demos and reference designs to kick start designs
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Low Power FPGA Featuring Hardened MIPI D-PHY, LVDS, SLVS, SubLVDS, & Open LDI Bridging
CrossLink
*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY*15 programmable source synchronous I/O pairs for camera and display interfacing*Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch
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PLD For Bridging, Infinitely Reconfigurable I/O Expansion.
MachXO
*Up to 27.6 Kbits sysMEM™ embedded block RAM and up to 7.7Kbits distributed RAM*SRAM based logic can be reconfigured in milliseconds using JTAG port*IOs support LVCMOS, LVTTL, PCI, LVDS, Bus-LVDS, LVPECL, RSDS*Up to two analog PLLs per device that enable clock multiplication, division, and phase shifting*Available in TQFP, csBGA, caBGA and ftBGA packages
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Break The Rules Of Power, Size And Cost In Your Connectivity And Acceleration Applications
ECP5 / ECP5-5G
*Up to 3.2 Gbps SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G*Up to 4 channels per device in dual channel blocks for higher granularity*Enhanced DSP blocks provide 2x resource improvement for symmetrical filters*Single event upset (SEU) mitigation support*Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input/output interfaces
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Best In Class, Easy To Use Design Software
Lattice Radiant Software
Full Featured, Easy to Use Tool Suite - Lattice Radiant software offers all the best in class tools and features to help users develop their FPGA applications efficiently and effectively. Powerful yet intuitive tools provide fast design starts and precise implementation.
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Manage Power, Thermal & Control Planes In Real Time
Platform Manager 2 & L-ASC10
*Full fault coverage – monitor all rails and temperature nodes*Manage from 10 to 80 supplies using just the required number of L-ASC10 hardware management expanders*Minimize fault propagation by enabling individual hardware management sub-blocks (power, thermal & control path) to respond to faults in other blocks within nano-seconds*Save CPLD I/O pins by eliminating the need to monitor power-good signals of DC-DC converters*Reliable power & thermal fault detection in hardware, as opposed to software routines
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Get Flexible, Get FlexiFLASH
LatticeXP2
*Up to 885 Kbits sysMEM™ embedded block RAM and up to 83 Kbits distributed RAM*sysCLOCK™ PLLs up to four analog PLLs per device that enable clock multiply, divide and phase shifting*Three to eight sysDSP blocks for high performance multiply and accumulate.*Pre-engineered source synchronous IOs for DDR/DDR2 up to 200 MHz and 7:1 LVDS interface support up to 600 Mbps*Available in csBGA, TQFP, PQFP and BGA packaging
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Enabling Low Power, High Reliability, And High Performance Design
Lattice Nexus Platform
The Lattice Nexus FPGA platform combines Lattice’s long-standing low power FPGA expertise with leading 28nm FD-SOI semiconductor manufacturing technology. With this platform, Lattice enables the rapid development of multiple device families that deliver low power, high performance, high reliability and small form factor.
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Advanced General Purpose FPGA
CertusPro-NX
*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
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Rapidly Compile Networks For Implementation On Lattice SensAI IP Cores
Neural Network Compiler
Analyze networks for fit in the chosen number of engines and allocated memory. After compilation, simulate networks for functionality and performance prior to testing in hardware. Graphical display of networks supports analysis and understanding.
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Bridging And I/O Expansion Versatility. Rapid Hardware Acceleration For Improved Signal Control.
MachXO2
*Up to 256 kbits of user Flash memory and up to 240 kbits sysMEM™ embedded block RAM*Up to 334 hot-socketable IOs that avoid excess leakage*Programmable through JTAG, SPI, I2C or Wishbone*TransFR feature allows in-field design update without interrupting equipment operation*Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more
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Integrated Board Power Management Functions For The Forward Thinking Engineer
Power Manager II
*Up to 12 differential voltage sensors with immunity to noise on ground plane*Voltage trimming to within 1%*Ruggedized CPLD with up to 48 macrocells for sequencing and supervisory signal logic*Large operating power supply range (3.3 V + 20% to 3.3 V -15%)*Up to 4 High-Voltage MOSFET Driver Outputs*Voltage Measurement with 10-bit ADC through I2C*Up to 8 On-chip DACs for Margining and Trimming
